Processors often employ content addressable memories (CAMs) to store data structures that are frequently searched. Typically, compare data (e.g. a memory address or cache tag) is supplied to a CAM, which then searches its entries in parallel for data matching the compare data. If an entry stores data matching the compare data, the CAM provides an indicator identifying the entry. The parallel search capability of the CAM renders it well-suited for high-speed searching applications, such as in cache tag arrays used to determine if a cache stores data associated with an identified memory address. In order to enhance access speed, the CAM may be configured so that data may be written to the CAM concurrently with a search of the CAM for compare data. The concurrent write and compare operations can result in an erroneous indication that the CAM stores the compare data when the CAM entry that matches the compare data is the target of the write operation. Conventional CAM implementations avoid this issue by employing circuitry that forces the concurrent compare operation to take place after the write data is written to the corresponding CAM entry. However, such circuitry increases the circuit area and power consumed by the processor.
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